1. Field of the Invention
The present invention relates to a method of testing an operation of a semiconductor memory device and a semiconductor memory device which can be subjected to such an operation test, and more particularly, to a method of acceleratedly testing a read operation of a dynamic random access memory (hereinafter referred to as "DRAM") having a hierarchical bit line (divided bit line) structure.
2. Description of the Background Art
A DRAM having a so-called hierarchical bit line structure has been proposed for the purpose of implementing large storage capacity with small chip area. In this DRAM, a plurality of sub-bit line pairs are provided corresponding to a single main bit line pair, and each sub-bit line pair is connected through two selection transistors to the main bit line. A semiconductor memory device with a hierarchical bit line structure including a main bit line pair having at most 1/4 parasitic capacitance per unit length of a sub-bit line pair has been already disclosed in Japanese Patent Laying-Open No. 6-349267.
With increase in capacity of a semiconductor memory device, time required for an operation test thereof increases. Therefore, an accelerated testing method which can be carried out reliably for a short time is becoming important. In particular, since a semiconductor memory device with a hierarchical bit line structure generally has large storage capacity, it conventionally takes a lot of time to carry out various tests of a read operation margin, a read noise margin, a sensing operation margin or the like thereof.